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VN5E050J-E
Single channel high side driver for automotive applications
Features
Max supply voltage Operating voltage range Max on-state resistance (per ch.) Current limitation (typ) Off state supply current
1. Typical value with all loads connected.
VCC VCC RON ILIMH IS
41V 4.5 to 28V 50 m 27A 2 A(1)
PowerSSO-12
Application
General - Inrush current active management by power limitation - Very low stand-by current - 3.0V CMOS compatible inputs - Optimized electromagnetic emissions - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC european directive Diagnostic functions - Open Drain status output - On-state open load detection - Off-state open load detection - Output short to VCC detection - Overload and short to ground (power limitation) indication - Thermal shutdown indication Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self-limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Over-temperature shutdown with autorestart (thermal shutdown) - Reverse battery protected (a) - Electrostatic discharge protection
All types of resistive, inductive and capacitive loads.
Description
The VN5E050J-E is a single channel high-side driver manufactured in the ST proprietary VIPower M0-5 technology and housed in the tiny PowerSSO-12 package. The VN5E050J-E is designed to drive automotive grounded loads delivering protection, diagnostics and easy 3V and 5V CMOS-compatible interface with any microcontroller. The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, over-temperature shut-off with autorestart and over-voltage active clamp. A dedicated active low digital status pin is associated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short-circuit to ground, over-temperature indication, short-circuit to VCC diagnosis and ON & OFF state open-load detection. The diagnostic feedback of the whole device can be disabled by pulling the STAT_DIS pin up, thus allowing wired-ORing with other similar devices.
a. See Application schematic.
February 2008
Rev 2
1/34
www.st.com 34
Contents
VN5E050J-E
Contents
1 2 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1 3.1.2 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
3.2 3.3 3.4 3.5
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 5.2 5.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/34
VN5E050J-E
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V; Tj = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin (VSD=0V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Openload detection (8V3/34
List of figures
VN5E050J-E
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open Load with external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Open Load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Maximum turn-Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 27 Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 27 PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-12 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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VN5E050J-E
Block diagram and pin configuration
1
Block diagram and pin configuration
Figure 1. Block diagram
VCC S ig n a l C la m p
U nd e rvo lta g e
C ontrol & D ia gnos tic
P ower C la m p
IN
D R IV E R V ON L im ita tio n O ve r te m p . C urre nt L im ita tio n O F F S ta te O p e n lo a d O N S ta te O p e n lo a d
S T_ D IS
ST
OUT
L O G IC
O V E R L O A D P R O T E C T IO N (A C T IV E P O W E R L IM IT A T IO N)
GND
Table 1.
Name VCC
Pin function
Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Open Drain digital diagnostic pin. Active high CMOS compatible pin, to disable the STATUS pin.
OUTPUT GND INPUT STATUS STAT_DIS
5/34
Block diagram and pin configuration Figure 2. Configuration diagram (top view)
VN5E050J-E
TAB = Vcc NC GND INPUT STAT_DIS STATUS N.C. 1 2 3 4 5 6 12 11 10 9 8 7 N.C. OUTPUT OUTPUT OUTPUT OUTPUT N.C.
Table 2.
Suggested connections for unused and not connected pins
Status X Not allowed N.C. X X Output X Not allowed Input X Through 10K resistor STAT_DIS X Through 10K resistor
Connection / pin Floating To ground
6/34
VN5E050J-E
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS VCC VF VCC
ISD STAT_DIS VSD IIN INPUT VIN GND IGND STATUS OUTPUT
IOUT VOUT
ISTAT
VSTAT
Note:
VF = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the "Absolute maximum ratings" tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in the "Absolute maximum ratings" tables for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3.
Symbol VCC -VCC -IGND IOUT -IOUT IIN ISTAT DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC status current
Absolute maximum ratings
Parameter Value 41 0.3 200 Internally limited 15 +10 / -1 +10 / -1 +10 / -1 104 Unit V V mA A A mA mA mA mJ
ISTAT_DIS DC status disable current EMAX Maximum switching energy (L=3mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) )
7/34
Electrical specifications Table 3.
Symbol
VN5E050J-E
Absolute maximum ratings (continued)
Parameter Electrostatic discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - STATUS - STAT_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value Unit
VESD
4000 4000 4000 5000 5000 750 -40 to 150 - 55 to 150
V V V V V V C C
VESD Tj Tstg
2.2
Thermal data
Table 4.
Symbol Rthj-case Rthj-amb
Thermal data
Parameter Thermal resistance junction-case (max) (with one channel ON) Thermal resistance junction-ambient (max) Value 2.7 See Figure 36 Unit C/W C/W
8/34
VN5E050J-E
Electrical specifications
2.3
Electrical characteristics
Values specified in this section are for 8VSymbol VCC VUSD VUSDhyst
Power section
Parameter Operating supply voltage Undervoltage shutdown Undervoltage shutdown hysteresis On state resistance Clamp voltage IOUT=2A; Tj=25C IOUT=2A; Tj=150C IOUT=2A; VCC=5V; Tj=25C IS = 20 mA Off State; VCC=13V; VIN=VOUT=0V; Tj=25C On State; VIN=5V; VCC=13V; IOUT=0A VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C 0 0 41 46 Test conditions Min. 4.5 Typ. 13 3.5 0.5 50 100 65 52 Max. 28 4.5 Unit V V V m m m V
RON Vclamp
IS
Supply current
2(1) 3
5(1) 6
A mA
IL(off1)
Off state output current
0.01
3 5 0.7
A A V
VF
Output - VCC diode voltage -IOUT=2A; Tj=150C
1. PowerMOS leakage included.
Table 6.
Symbol td(on) td(off) dVOUT/dt(on) dVOUT/dt(off) WON WOFF
Switching (VCC = 13V; Tj = 25C)
Parameter Test conditions Min. Typ. 20 40 See Figure 26. See Figure 28. 0.21 0.28 Max. Unit s s V/s V/s mJ mJ
Turn-On delay time RL=6.5 (see Figure 6.) Turn-Off delay time RL=6.5 (see Figure 6.) Turn-On voltage slope Turn-Off voltage slope Switching energy losses during twon Switching energy losses during twoff RL=6.5 RL=6.5 RL=6.5 (see Figure 6.) RL=6.5 (see Figure 6.)
9/34
Electrical specifications Table 7.
Symbol VSTAT ILSTAT CSTAT VSCL
VN5E050J-E
Status pin (VSD=0V)
Parameter Status low output voltage Status leakage current Status pin input capacitance Status clamp voltage Test conditions ISTAT= 1.6 mA, VSD=0V Normal operation or VSD=5V, VSTAT= 5V Normal operation or VSD=5V, VSTAT= 5V ISTAT= 1mA ISTAT= - 1mA 5.5 -0.7 Min. Typ. Max. 0.5 10 100 7 Unit V A pF V V
Table 8.
Symbol IlimH IlimL TTSD TR TRS THYST tSDL VDEMAG
Protections (1)
Parameter DC short circuit current Test conditions VCC=13V; 5VTTSD ( see Figure 4.) VCC-41 VCC-46 20 VCC-52 C s V
Short circuit current VCC=13V; TR7 175 TRS + 5
Turn-off output voltage IOUT=2A; VIN=0; L=6mH clamp Output voltage drop limitation IOUT=0.1A; Tj= -40C...+150C (see Figure 5.)
VON
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
10/34
VN5E050J-E Table 9.
Symbol IOL tDOL(on)
Electrical specifications Open load detection (8VParameter Openload ON state detection threshold Openload ON state detection delay Delay between INPUT falling edge and STATUS rising edge in openload condition Openload OFF state voltage detection threshold Test conditions VIN = 5V IOUT = 0A, VCC=13V (see Figure 4.) Min 10 Typ Max 70 200 Unit mA s
tPOL
IOUT = 0A (see Figure 4.)
200
500
1200
s
VOL
VIN = 0V
2
4
V
Output short circuit to tDSTKON VCC detection delay at turn Off IL(off2) Off state output current Delay response from output rising edge to STATUS falling edge in open load
See Figure 4. VIN= 0V; VOUT= 4V (see Section 3.4: Open load detection in Off state)
180
tPOL
s
-75
0
A
td_vol
VIN= 0V; VOUT= 4V
20
s
Table 10.
Symbol VIL IIL VIH IIH VI(hyst) VICL VSDL ISDL VSDH ISDH
Logic input
Parameter Input low level Low level input current Input high level High level input current Input hysteresis voltage Input clamp voltage STAT_DIS low level voltage Low level STAT_DIS current STAT_DIS high level voltage High level STAT_DIS current VSD = 2.1 V 0.25 ISD= 1mA ISD= -1mA 5.5 -0.7 7 VSD = 0.9 V 1 2.1 10 IIN = 1mA IIN = -1mA VIN = 2.1 V 0.25 5.5 7 -0.7 0.9 VIN =0.9 V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
VSD(hyst) STAT_DIS hysteresis voltage VSDCL STAT_DIS clamp voltage
11/34
Electrical specifications Figure 4. Status timings
VN5E050J-E
OPEN LOAD STATUS TIMING (without external pull-up) VIN IOUT < IOL VOUT < VOL
OPEN LOAD STATUS TIMING (with external pull-up) VIN IOUT < IOL VOUT > VOL
VSTAT tDOL(on) tPOL
VSTAT tDOL(on)
OUTPUT STUCK TO VCC VIN IOUT > IOL VOUT > VOL
OVER TEMP STATUS TIMING Tj > TTSD VIN
VSTAT tDOL(on) tDSTKON
VSTAT tSDL tSDL
Figure 5.
Output voltage drop limitation
Vcc-Vout
Tj=150oC Tj=25oC Tj=-40oC
Von Iout
Von/Ron(T)
12/34
VN5E050J-E Figure 6. Switching characteristics
VOUT
tWon tWoff
Electrical specifications
80% dVOUT/dt(on) tr 10%
90% dVOUT/dt(off) tf t
INPUT td(on) td(off)
t
Table 11.
Truth table
INPUT L H L H L H H OUTPUT L H L L L L X (no power limitation) Cycling (power limitation) H H L H STATUS (VSD=0V)(1) H H H L X X H L L(2) H H(3) L
Conditions Normal Operation Overtemperature Undervoltage
Overload & Short circuit to GND
H L H L H
Output voltage > VOL Output current < IOL
1. If the VSD is high, the STATUS pin is in a high impedance. 2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge. 3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
13/34
Electrical specifications Table 12.
ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) III C C C C C C
VN5E050J-E
Electrical transient requirements
Test levels (1) III -75 V +37 V -100 V +75 V -6 V +65 V IV -100 V +50 V -150 V +100 V -7 V +87 V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Test level results (1) IV C C C C C C Burst cycle/pulse repetition time Delays and impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2
0.5 s 0.2 s 90 ms 90 ms
5s 5s 100 ms 100 ms
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
14/34
VN5E050J-E
Electrical specifications
2.4
Waveforms
Figure 7. Normal operation
Normal operation
INPUT Nominal load Nominal load
IOUT
VSTATUS
VST_DIS
Figure 8.
Undervoltage shutdown
Undervoltage shut-down
VUSDhyst
VCC
VUSD
INPUT
IOUT
UNDEFINED
VSTATUS
VST_DIS
15/34
Electrical specifications Figure 9. Overload or Short to GND
VN5E050J-E
Overload or Short to GND
INPUT ILimH > IOUT
Power Limitation Thermal cycling ILimL >
VSTATUS
VST_DIS
Figure 10. Intermittent Overload
Intermittent Overload
INPUT ILimH > IOUT
Overload ILimL > Nominal load
VSTATUS
VST_DIS
16/34
VN5E050J-E Figure 11. Open Load with external pull-up
Electrical specifications
Open Load with external pull-up
INPUT
VPU > VOL VOL
VOUT
IOUT tDOL(on) VSTATUS
VST_DIS
Figure 12. Open Load without external pull-up
Open Load without external pull-up
INPUT
VOUT IOUT < IOL IOUT IOL tDOL(on) VSTATUS tPOL
VST_DIS
17/34
Electrical specifications Figure 13. Short to VCC
VN5E050J-E
Short to V CC
Resistive Short to VCC Hard Short to VCC
INPUT
VOUT > VOL VOL IOUT > IOL
VOUT > VOL
VOUT
IOUT
IOL
IOUT < IOL
tDSTK(on) VSTATUS
tDOL(on)
VST_DIS
Figure 14. TJ evolution in Overload or Short to GND
TJ evolution in Overload or Short to GND
INPUT
Self-limitation of fast thermal transients
TTSD TR
THYST
TJ_START TJ ILimH > Power Limitation
< ILimL IOUT
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VN5E050J-E
Electrical specifications
2.5
Electrical characteristics curves
Figure 16. High level input current
Iih (A)
4,5
Figure 15. Off state output current
Iloff (nA)
1500
Vin=2.1V
1250
1000
Off State Vcc=13V Vin=Vout=0V
4
3,5 750 3 500 2,5
250
0 -50 -25 0 25 50 75 100 125 150 175
2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 17. Input clamp voltage
Vicl (V)
7
Figure 18. Input high level
Vih (V)
3
6,8
2,5
lin=1mA
2
6,6 1,5 6,4 1 6,2
0,5
6 -50 -25 0 25 50 75 100 125 150 175
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 19. Input low level
Vil (V)
2 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 -50 -25 0 25 50 75 100 125 150 175
Figure 20. Low level STAT_DIS current
Isdl (A)
5 4,5 4 3,5 3 2,5 2 1,5 1 -50 -25 0 25 50 75 100 125 150 175
Vsd= 0.9V
Tc (C)
Tc (C)
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Electrical specifications
VN5E050J-E
Figure 21. On state resistance vs Tcase
Ron (mOhm)
120
Figure 22. High level STAT_DIS current
Isdh (A)
5
100
Iout= 2A Vcc=13V
4,5
Vsd= 2.1V
80
4
60
3,5
40
3
20
2,5
0 -50 -25 0 25 50 75 100 125 150 175
2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 23. On state resistance vs VCC
Ron (mOhm)
100
Figure 24. Low level input current
Iil (A)
5 4,5
Tc=150C
80 4
Vin=0.9V
Tc=125C
60
3,5 3 2,5 2 1,5 1
Tc=25C
40
Tc=-40C
20 0 5 10 15 20 25 30 35
-50
-25
0
25
50
75
100
125
150
175
Vcc (V)
Tc (C)
Figure 25. ILIM vs Tcase
Ilimh (A)
40
Figure 26. Turn-On voltage slope
(dVout/dt )On (V/ms)
800
35
700
Vcc=13V RI=6.5 Ohm
Vcc=13V
30 600
25
500
20
400
15
300
10 -50 -25 0 25 50 75 100 125 150
200 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VN5E050J-E
Electrical specifications
Figure 27. Undervoltage shutdown
Vusd (V)
7
Figure 28. Turn-Off voltage slope
(dVout/dt )Off (V/ms)
500
6 400 5 300
Vcc=13V RI= 6.5 Ohm
4
3
200
2 100 1
0 -50 -25 0 25 50 75 100 125 150 175
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 29. STAT_DIS clamp voltage
Vsdcl(V)
10
Figure 30. High level STAT_DIS voltage
VsdH(V)
3
9
2,5
Isd = 1 mA
8 2 7 1,5 6 1 5 0,5
4
3 -50 -25 0 25 50 75 100 125 150 175
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 31. Low level STAT_DIS voltage
VsdL(V)
2,5
2
1,5
1
0,5
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
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Application information
VN5E050J-E
3
Application information
Figure 32. Application schematic
+5V
+5V VCC Rprot STAT_DIS
Dld Rprot MCU OUTPUT Rprot STATUS GND INPUT
VGND
RGND
DGND
3.1
3.1.1
GND protection network against reverse battery
Solution 1: resistor in the ground line (RGND only)
This solution can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (- CC) / (-IGND) V
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND.
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VN5E050J-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used (see below).
3.1.2
Solution 2: diode (DGND) in the ground line
A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (~600mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests that a resistor (Rprot) be inserted in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k . Recommended Rprot value is 10k.
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Application information
VN5E050J-E
3.4
Open load detection in Off state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between the OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. No false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT= (VPU/(RL+RPU))RLBecause Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical characteristics section. Figure 33. Open load detection in Off state
V batt. VCC R PU INP UT DRI VER + LOGI C OUT + STATUS VOL R IL(off2) VPU
RL
GROUND
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VN5E050J-E
Application information
3.5
Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-Off current versus inductance
100
A B C
10
I (A) 1 0,1 1 L (mH) 10 100
A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data
VN5E050J-E
4
4.1
Package and PCB thermal data
PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/W)
65 60 55 50 45 40 35 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
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VN5E050J-E
Package and PCB thermal data
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse
ZTH (C/W)
100
Footprint 2 cm2 8 cm2
10
1
0,1 0,001
0,01
0,1
1 Time (s)
10
100
1000
Equation 1: pulse calculation formula Z TH =R TH +Z THtp ( 1 - ) where = tP/T Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12 (a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
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Package and PCB thermal data Table 13. Thermal parameter
Footprint 0.7 2.8 3 8 22 26 0.001 0.0025 0.0166 0.2 0.27 3 0.1 0.8 6 8 15 20 2
VN5E050J-E
Area/island (cm2) R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
8
7 10 15
0.1 1 9
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VN5E050J-E
Package and packing information
5
5.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 39. PowerSSO-12 package dimensions
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Package and packing information Table 14. PowerSSO-12 mechanical data
Millimeters Symbol Min. A A1 A2 B C D E e H h L k X Y ddd 5.800 0.250 0.400 0 2.200 2.900 1.250 0.000 1.100 0.230 0.190 4.800 3.800 0.800 Typ.
VN5E050J-E
Max. 1.620 0.100 1.650 0.410 0.250 5.000 4.000
6.200 0.500 1.270 8 2.800 3.500 0.100
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VN5E050J-E
Package and packing information
5.3
Packing information
Figure 40. PowerSSO-12 tube shipment (no suffix)
B C
A
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm.
100 2000 532 1.85 6.75 0.6
Figure 41. PowerSSO-12 tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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Order codes
VN5E050J-E
6
Order codes
Table 15. Device summary
Order codes Package Tube PowerSSO-12 VN5E050J-E Tape and reel VN5E050JTR-E
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VN5E050J-E
Revision history
7
Revision history
Table 16.
Date 31-Aug-2007
Document revision history
Revision 1 Initial release. Document restructured. Changed Description on cover page. Table 9: Open load detection (8V19-Feb-2008
2
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VN5E050J-E
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